Development of I2C: Developed the Agent (driver, monitor and Sequencer) using System Verilog and implemented using UVM. Setup the MONITOR and SCOREBOARD to check the data integrity Between the RTL and Bench. Setup the COVERAGE MODEL to check CODE COVERAGE and FUNCTIONAL COVERAGE and documented the Test Plan. Coded Test cases to verify the functionality of CSI2. Created verification plan, test plan to cover all the cases. Developed the IP LEVEL BENCH for CSI2 using UVM. The D-PHY protocol defines the signals, timing, and functionality required for efficient communication Between Tx and Rx interface. MIPI - CSI2 Rx IP Verification CSI2 is a Camera Serial Interface which interfaces to Camera via CSI2-Tx and D-PHY Interface. HfO2 and Polysilicon have been deposited for gate formation at center of Nanowire. Boron doped silicon horizontal Nano wire of 20nm wide and 100nm long has been grown on SOI wafer. Design of Junction less Nano wire transistor in Sentaurus Process. Optical generation has been measured by using Synopsys TCAD and found to be efficient. New Mercury Cadmium Telluride Nanowire based photo detector has been implemented horizontally Simulations have been carried out using optical model. Master of Science thesis on “Exploration of 3D Nanowire Image sensor and circuitry to enable logic and sensing in single chip”. TCAD based simulations of 3D Image sensor, integration of sensor and circuitry in a single chip. Programming Languages: C, Assembly Language, Embedded TCAD Tools Synopsys: Sentaurus Process, Sentaurus Device, Sentaurus Structure Hardware Platforms: Basys, Basys 2, Spartan 3E, Spartan 2, Vertex5, Arduino.ĮDA Tools Cadence: SOC Encounter, RTL Compiler, Virtuoso, Layout XL, Spectre 
Knowledge in Designing Nano scale sensors and exploring new devices. Hands on experience with clean room and fabrication process.Expert in handling bunch of Test cases, reporting the bugs, running regression testing and coverage.Strong knowledge ASIC/ FPGA pre silicon verification with Full constraint random testing, coverage based verification.
Strong expertise in IP Verification, SV Assertions, Functional Coverage and Low Power Verification.Well versed with System Verilog and progressive experience with UVM test methodologies.Over 7 years of experience in ASIC Verification, RTL Design including design specification, RTL coding, simulation, synthesis, logic equivalence check and power analysis.
0 kommentar(er)
